The present invention relates to a solid-state image sensor such as CCD (Charge Coupled Device memory) having high detection sensitivity, and to a manufacturing method therefor.
FIG. 4A is a plan view showing main part of a CCD according to the prior art. In the figure, reference numeral 41 denotes a horizontal transfer section, 42 denotes a horizontal power output gate, 43 denotes a reset gate, 44 denotes a reset drain, 45 denotes a detector MOSFET (MOS Field Effect Transistor), 46 denotes a floating diffusion layer (hereinafter, referred to as FD), 47 and 57 denote contact holes, 48 denotes an aluminum line, and 50 denotes a gate electrode of the detector MOSFET 45. This detector MOSFET 45 is a part of a detector circuit for detecting potential changes of the FD 46. The FD 46 is formed of an N+ layer, and the N+ layer is made by exposing part where the FD 46 is to be formed with photoresist by patterning, and performing ion implantation to the exposed part.
FIG. 4B is a sectional view taken along the line Bxe2x80x94B of FIG. 4A, where reference numeral 51 denotes a P-type semiconductor substrate and 52 denotes field oxide. As shown in FIG. 4B, a contact hole 47 is formed above the FD 46, and a contact hole 57 is also formed above an FD 46 side end portion of the gate electrode 50. The aluminum line 48 is formed at the contact holes 47, 57, by which the FD 46 and the gate electrode 50 are connected to each other by the aluminum line 48.
In the CCD of this constitution, a reset pulse voltage applied to a reset gate 43 is made high level to reset the FD 46, and the reset pulse voltage is made low level to transfer signal charges from the horizontal transfer section 41 to the FD 46. In this case, assuming that the entire capacitance containing the gate electrode 50 of the detector MOSFET 45 connected to the FD 46 is Ct and that the amount of transferred signal charges is Q, then there arises a potential change of xcex94Vfd=Q/Ct in the FD 46 and the potential change is detected by the detector MOSFET 45. Also, when the gain of the detector circuit having the detector MOSFET 45 is assumed to be G, the detection sensitivity of the detector circuit becomes xcex94Vout=Gxc2x7Q/Ct, where a voltage change proportional to the signal charge Q is outputted to the detector circuit.
In this case, capacitances composing the Ct principally includes an FDxe2x80x94reset gate junction capacitance Cfr, an FDxe2x80x94horizontal output gate junction capacitance Cog, a gate capacitance Cg of the detector MOSFET, an FDxe2x80x94semiconductor substrate junction capacitance Cfd, an aluminum wiring capacitance Cmr and the like. That is, the entire capacitance Ct containing the gate electrode 50 of the detector MOSFET 45 connected to the FD 46 is Ct=Cfr+Cog+Cg+Cfd+Cmr. Therefore, if the gain G of the detector circuit is constant, then the detection sensitivity can be made higher more and more with Cfd smaller. Since the capacitance Cfd of the FD 46 can be considered proportional to the area of the FD 46, the area of the FD 46 needs to be reduced as much as possible in order to achieve a high detection sensitivity.
FIG. 5A is a plan view showing main part of another CCD according to the prior art, and FIG. 5B is a sectional view taken along the line 5Bxe2x80x945B of FIG. 5A. FIGS. 5A and 5B are different from the prior art example of FIGS. 4A and 4B in that a gate electrode 150 of a detector MOSFET 145 is formed so as to extend to above an FD 146, and that aluminum line 148 formed at one contact hole 147 interconnects the FD 146 and the gate electrode 150. Therefore, in FIGS. 5A and 5B, the same component parts as those of FIGS. 4A and 4B are designated by the same reference numerals and omitted in description.
For manufacturing methods of the prior art CCDs, because it is difficult to further reduce the area of the FD 46, 146, the detection sensitivity of the charge detector circuit cannot be enhanced. That is, there is a problem that signal charges transferred from the horizontal transfer section 41 to the FD 46 cannot be detected at high sensitivity. In more detail, since the FD 46, 146 and the contact hole 47, 147 are formed by patterning with photoresist, there has been a need for ensuring alignment margins d1, d2 for the FD 46, 146 and the contact hole 47, 147. The alignment margin d should be 0.2-0.4 xcexcm or so, taking into consideration variations in line widths of the aluminum lines 48, 148 and the FD 46, 146 as well as in alignment. However, because the FD 46, 146 is sized about 1-2 xcexcmxe2x96xa1, the alignment margins d1, d2 are as large as 10-25% of the FD 46, 146, making it impossible to reduce the area of the FD 46, 146.
Therefore, an object of the present invention is to provide a CCD, as well as its manufacturing method, which makes it possible to reduce the area of the FD and to detect signal charges of the FD at high sensitivity.
In order to achieve the above object, there is provided a solid-state image sensor comprising: a first-conductive-type semiconductor substrate; a charge transfer section formed on the first-conductive-type semiconductor substrate; a second-conductive-type floating diffusion layer for receiving signal charges from the charge transfer section; and a detector transistor for detecting a potential change of the second-conductive-type floating diffusion layer, wherein
an opening is formed in a gate electrode of the detector transistor;
the gate electrode of the detector transistor extends toward the second-conductive-type floating diffusion layer 26 and the opening 30a is positioned above the second-conductive-type floating diffusion layer 26.
In this solid-state image sensor according to the invention, since the opening formed in the gate electrode of the detector transistor is positioned above the floating diffusion layer of the second-conductive-type floating diffusion layer, forming a metal line above the opening of the gate electrode allows self alignment to be achieved, by which the second-conductive-type floating diffusion layer and the metal line are connected to each other. Therefore, the alignment margin between the second-conductive-type floating diffusion layer and the contact hole can be eliminated, so that the area of the second-conductive-type floating diffusion layer can be reduced. As a result, the junction capacitance between the second-conductive-type floating diffusion layer and the semiconductor substrate is decreased so that signal charges of the second-conductive-type floating diffusion layer can be detected at high sensitivity.
Also, there is provided a solid-state image sensor comprising: a first-conductive-type semiconductor substrate; a charge transfer section formed on the first-conductive-type semiconductor substrate; a second-conductive-type floating diffusion layer for receiving signal charges from the charge transfer section; and a detector transistor for detecting a potential change of the second-conductive-type floating diffusion layer, wherein
the detector transistor has discontinuous first and second gate electrodes;
an opening is formed in the first gate electrode; and
the opening is positioned above the second-conductive-type floating diffusion layer.
In this solid-state image sensor according to one embodiment of the invention, since the detector transistor has discontinuous first and second gate electrodes and the opening of the first gate electrode is positioned above the second-conductive-type floating diffusion layer, forming a metal line above the opening of the first gate electrode allows self alignment to be achieved, by which the second-conductive-type floating diffusion layer and the metal line are connected to each other. Therefore, the alignment margin between the second-conductive-type floating diffusion layer and the contact hole can be eliminated, so that the area of the second-conductive-type floating diffusion layer can be reduced. As a result, the junction capacitance between the second-conductive-type floating diffusion layer and the semiconductor substrate is decreased so that signal charges of the second-conductive-type floating diffusion layer can be detected at high sensitivity.
Also, there is provided a method for manufacturing the solid-state image sensor, comprising the steps of:
forming the gate electrode of the detector transistor by etching;
forming photoresist on the gate electrode and around the gate electrode so as to surround the opening of the gate electrode; and
performing ion implantation with the photoresist and the gate electrode used as a mask to form the second-conductive-type floating diffusion layer below the opening of the gate electrode.
In the solid-state image sensor manufacturing method of this invention, since ion implantation is performed with the photoresist and the gate electrode used as a mask so that the second-conductive-type floating diffusion layer is formed below the opening of the gate electrode, self alignment is achieved so that the alignment margin for the second-conductive-type floating diffusion layer can be eliminated.
In one embodiment of the present invention, the second-conductive-type floating diffusion layer is formed in self alignment below the opening of the gate electrode.
In this solid-state image sensor manufacturing method according to one embodiment of the invention, since the second-conductive-type floating diffusion layer is formed in self alignment, the process becomes efficient.
In one embodiment of the present invention, the solid-state image sensor manufacturing method further comprises steps of: forming a contact hole in a planarization layer so as to be positioned above the opening of the gate electrode, and forming a metal line in the contact hole, by which the second-conductive-type floating diffusion layer and the gate electrode to each other with the metal line.
In this solid-state image sensor manufacturing method according to one embodiment of the invention, the contact hole is formed in the planarization layer so as to be positioned above the opening of the gate electrode, and the metal line is formed at the contact hole, by which the second-conductive-type floating diffusion layer and the gate electrode are connected to each other with the metal line. Thus, self alignment is achieved so that the alignment margin between the second-conductive-type floating diffusion layer and the contact hole can be eliminated.
In one embodiment of the present invention, the solid-state image sensor manufacturing method further comprises steps of: forming the first and second gate electrodes of the detector transistor by etching; forming photoresist on the first gate electrode and around the first gate electrode so as to surround the opening of the first gate electrode; and performing ion implantation with the photoresist and the first gate electrode used as a mask to form the second-conductive-type floating diffusion layer below the opening of the first gate electrode.
In this solid-state image sensor manufacturing method according to one embodiment of the invention, since ion implantation is performed with the photoresist and the first gate electrode used as a mask so that the second-conductive-type floating diffusion layer is formed below the opening of the first gate electrode, self alignment is achieved so that the alignment margin for the second-conductive-type floating diffusion layer can be eliminated.
In one embodiment of the present invention, the first and second gate electrodes are formed in one step.
In this solid-state image sensor manufacturing method according to one embodiment of the invention, since the first and second gate electrodes are formed simultaneously by one step, the solid-state image sensor can be manufactured efficiently.
In one embodiment of the present invention, the second-conductive-type floating diffusion layer is formed in self alignment below the opening of the first gate electrode.
In this solid-state image sensor manufacturing method according to one embodiment of the invention, since the second-conductive-type floating diffusion layer is formed in self alignment, the process becomes more efficient.
In one embodiment of the present invention, the solid state image sensor manufacturing method further comprises steps of: forming a contact hole in a planarization layer so that the contact hole is positioned above the opening of the first gate electrode, and forming a metal line in the contact hole, by which the second-conductive-type floating diffusion layer and the first gate electrode are connected to each other with the metal line.
In this solid-state image sensor manufacturing method according to one embodiment of the invention, the contact hole is formed in the planarization layer so as to be positioned above the opening of the first gate electrode, and the metal line is formed at the contact hole, by which the second-conductive-type floating diffusion layer and the first gate electrode are connected to each other with the metal line. Thus, self alignment is achieved so that the alignment margin between the second-conductive-type floating diffusion layer and the contact hole can be eliminated.